CWE-1303
Non-Transparent Sharing of Microarchitectural Resources
Hardware structures shared across execution contexts (e.g., caches and branch predictors) can violate the expected architecture isolation between contexts.
CVE-2023-1998 (GCVE-0-2023-1998)
Vulnerability from cvelistv5
- CWE-1303 - Non-Transparent Sharing of Microarchitectural Resources
Vendor | Product | Version | ||
---|---|---|---|---|
Linux | Linux Kernel |
Version: 0 < 6.3 |
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We had noticed that on VMs of at least one major cloud provider, the kernel still left the victim process exposed to attacks in some cases even after enabling the spectre-BTI mitigation with prctl. The same behavior can be observed on a bare-metal machine when forcing the mitigation to IBRS on boot command line.\u003c/p\u003e\u003cp\u003eThis happened because when plain IBRS was enabled (not enhanced IBRS), the kernel had some logic that determined that STIBP was not needed. The IBRS bit implicitly protects against cross-thread branch target injection. However, with legacy IBRS, the IBRS bit was cleared on returning to userspace, due to performance reasons, which disabled the implicit STIBP and left userspace threads vulnerable to cross-thread branch target injection against which STIBP protects.\u003c/p\u003e\u003cbr\u003e" } ], "value": "The Linux kernel allows userspace processes to enable mitigations by calling prctl with PR_SET_SPECULATION_CTRL which disables the speculation feature as well as by using seccomp. We had noticed that on VMs of at least one major cloud provider, the kernel still left the victim process exposed to attacks in some cases even after enabling the spectre-BTI mitigation with prctl. The same behavior can be observed on a bare-metal machine when forcing the mitigation to IBRS on boot command line.\n\nThis happened because when plain IBRS was enabled (not enhanced IBRS), the kernel had some logic that determined that STIBP was not needed. The IBRS bit implicitly protects against cross-thread branch target injection. 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CVE-2023-38575 (GCVE-0-2023-38575)
Vulnerability from cvelistv5
- information disclosure
- CWE-1303 - Non-Transparent Sharing of Microarchitectural Resources
Vendor | Product | Version | ||
---|---|---|---|---|
n/a | Intel(R) Processors |
Version: some Intel(R) Processors |
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CVE-2023-40540 (GCVE-0-2023-40540)
Vulnerability from cvelistv5
- information disclosure
- CWE-1303 - Non-Transparent Sharing of Microarchitectural Resources
Vendor | Product | Version | ||
---|---|---|---|---|
n/a | Intel(R) NUC BIOS firmware |
Version: some Intel(R) NUC BIOS firmware |
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Mitigation
Phase: Architecture and Design
Description:
- Microarchitectural covert channels can be addressed using a mixture of hardware and software mitigation techniques. These include partitioned caches, new barrier and flush instructions, and disabling high resolution performance counters and timers.
Mitigation
Phase: Requirements
Description:
- Microarchitectural covert channels can be addressed using a mixture of hardware and software mitigation techniques. These include partitioned caches, new barrier and flush instructions, and disabling high resolution performance counters and timers.
CAPEC-663: Exploitation of Transient Instruction Execution
An adversary exploits a hardware design flaw in a CPU implementation of transient instruction execution to expose sensitive data and bypass/subvert access control over restricted resources. Typically, the adversary conducts a covert channel attack to target non-discarded microarchitectural changes caused by transient executions such as speculative execution, branch prediction, instruction pipelining, and/or out-of-order execution. The transient execution results in a series of instructions (gadgets) which construct covert channel and access/transfer the secret data.