CWE-1342

Information Exposure through Microarchitectural State after Transient Execution

The processor does not properly clear microarchitectural state after incorrect microcode assists or speculative execution, resulting in transient execution.

CVE-2022-40982 (GCVE-0-2022-40982)
Vulnerability from cvelistv5
Published
2023-08-11 02:37
Modified
2025-02-13 16:33
Severity ?
6.5 (Medium) - CVSS:3.1/AV:L/AC:L/PR:L/UI:N/S:C/C:H/I:N/A:N
CWE
  • information disclosure
  • CWE-1342 - Information exposure through microarchitectural state after transient execution
Summary
Information exposure through microarchitectural state after transient execution in certain vector execution units for some Intel(R) Processors may allow an authenticated user to potentially enable information disclosure via local access.
References
Impacted products
Vendor Product Version
n/a Intel(R) Processors Version: See references
Show details on NVD website

To clipboard 

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CVE-2023-28746 (GCVE-0-2023-28746)
Vulnerability from cvelistv5
Published
2024-03-14 16:45
Modified
2025-04-26 20:03
Severity ?
6.5 (Medium) - CVSS:3.1/AV:L/AC:L/PR:L/UI:N/S:C/C:H/I:N/A:N
CWE
  • information disclosure
  • CWE-1342 - Information exposure through microarchitectural state after transient execution from some register files
Summary
Information exposure through microarchitectural state after transient execution from some register files for some Intel(R) Atom(R) Processors may allow an authenticated user to potentially enable information disclosure via local access.
References
Impacted products
Vendor Product Version
n/a Intel(R) Atom(R) Processors Version: See references
Show details on NVD website

To clipboard 

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Mitigation

Phases: Architecture and Design, Requirements

Description:

  • Hardware ensures that no illegal data flows from faulting micro-ops exists at the microarchitectural level.
Mitigation

Phase: Build and Compilation

Description:

  • Include instructions that explicitly remove traces of unneeded computations from software interactions with microarchitectural elements e.g. lfence, sfence, mfence, clflush.
CAPEC-696: Load Value Injection

An adversary exploits a hardware design flaw in a CPU implementation of transient instruction execution in which a faulting or assisted load instruction transiently forwards adversary-controlled data from microarchitectural buffers. By inducing a page fault or microcode assist during victim execution, an adversary can force legitimate victim execution to operate on the adversary-controlled data which is stored in the microarchitectural buffers. The adversary can then use existing code gadgets and side channel analysis to discover victim secrets that have not yet been flushed from microarchitectural state or hijack the system control flow.

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