CWE-1421
Exposure of Sensitive Information in Shared Microarchitectural Structures during Transient Execution
A processor event may allow transient operations to access architecturally restricted data (for example, in another address space) in a shared microarchitectural structure (for example, a CPU cache), potentially exposing the data over a covert channel.
CVE-2024-28956 (GCVE-0-2024-28956)
Vulnerability from cvelistv5
- Information Disclosure
- CWE-1421 - Exposure of Sensitive Information in Shared Microarchitectural Structures during Transient Execution
Vendor | Product | Version | ||
---|---|---|---|---|
n/a | Intel(R) Processors |
Version: See references |
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CVE-2024-36350 (GCVE-0-2024-36350)
Vulnerability from cvelistv5
- CWE-1421 - Exposure of Sensitive Information in Shared Microarchitectural Structures during Transient Execution
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CVE-2024-36357 (GCVE-0-2024-36357)
Vulnerability from cvelistv5
- CWE-1421 - Exposure of Sensitive Information in Shared Microarchitectural Structures during Transient Execution
Vendor | Product | Version | ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
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► | AMD | AMD EPYC™ 7003 Series Processors | ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
|
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CVE-2024-38296 (GCVE-0-2024-38296)
Vulnerability from cvelistv5
- CWE-1421 - Exposure of Sensitive Information in Shared Microarchitectural Structures during Transient Execution
Vendor | Product | Version | ||
---|---|---|---|---|
Dell | Edge Gateway 5200 |
Version: N/A ≤ |
{ "containers": { "adp": [ { "affected": [ { "cpes": [ "cpe:2.3:o:dell:edge_gateway_5200_firmware:*:*:*:*:*:*:*:*" ], "defaultStatus": "unknown", "product": "edge_gateway_5200_firmware", "vendor": "dell", "versions": [ { "lessThan": "12.0.94.2380", "status": "affected", "version": "0", "versionType": "semver" } ] } ], "metrics": [ { "other": { "content": { "id": "CVE-2024-38296", "options": [ { "Exploitation": "none" }, { "Automatable": "no" }, { "Technical Impact": "total" } ], "role": "CISA Coordinator", "timestamp": "2024-11-25T18:18:21.316783Z", "version": "2.0.3" }, "type": "ssvc" } } ], "providerMetadata": { "dateUpdated": "2024-11-25T18:20:39.113Z", "orgId": "134c704f-9b21-4f2e-91b3-4a467353bcc0", "shortName": "CISA-ADP" }, "title": "CISA ADP Vulnrichment" } ], "cna": { "affected": [ { "defaultStatus": "unaffected", "product": "Edge Gateway 5200", "vendor": "Dell", "versions": [ { "lessThan": "12.0.94.2380", "status": "affected", "version": "N/A", "versionType": "semver" } ] } ], "credits": [ { "lang": "en", "type": "finder", "value": "Dell would like to thank the Eclypsium Research Team for reporting this issue" } ], "datePublic": "2024-11-21T06:30:00.000Z", "descriptions": [ { "lang": "en", "supportingMedia": [ { "base64": false, "type": "text/html", "value": "Dell Edge Gateway 3200, versions prior to 15.40.30.2879, and Edge Gateway 5200, versions prior to 12.0.94.2380, contain an Exposure of Sensitive Information in Shared Microarchitectural Structures during Transient Execution vulnerability. A high privileged attacker with local access could potentially exploit this vulnerability, leading to information exposure." } ], "value": "Dell Edge Gateway 3200, versions prior to 15.40.30.2879, and Edge Gateway 5200, versions prior to 12.0.94.2380, contain an Exposure of Sensitive Information in Shared Microarchitectural Structures during Transient Execution vulnerability. A high privileged attacker with local access could potentially exploit this vulnerability, leading to information exposure." } ], "metrics": [ { "cvssV3_1": { "attackComplexity": "LOW", "attackVector": "LOCAL", "availabilityImpact": "HIGH", "baseScore": 6.7, "baseSeverity": "MEDIUM", "confidentialityImpact": "HIGH", "integrityImpact": "HIGH", "privilegesRequired": "HIGH", "scope": "UNCHANGED", "userInteraction": "NONE", "vectorString": "CVSS:3.1/AV:L/AC:L/PR:H/UI:N/S:U/C:H/I:H/A:H", "version": "3.1" }, "format": "CVSS", "scenarios": [ { "lang": "en", "value": "GENERAL" } ] } ], "problemTypes": [ { "descriptions": [ { "cweId": "CWE-1421", "description": "CWE-1421: Exposure of Sensitive Information in Shared Microarchitectural Structures during Transient Execution", "lang": "en", "type": "CWE" } ] } ], "providerMetadata": { "dateUpdated": "2024-12-09T15:03:06.924Z", "orgId": "c550e75a-17ff-4988-97f0-544cde3820fe", "shortName": "dell" }, "references": [ { "tags": [ "vendor-advisory" ], "url": "https://www.dell.com/support/kbdoc/en-us/000250949/dsa-2024-345-security-update-for-dell-networking-edge-gateway-5200-vulnerability" } ], "source": { "discovery": "UNKNOWN" }, "x_generator": { "engine": "Vulnogram 0.2.0" } } }, "cveMetadata": { "assignerOrgId": "c550e75a-17ff-4988-97f0-544cde3820fe", "assignerShortName": "dell", "cveId": "CVE-2024-38296", "datePublished": "2024-11-22T02:58:27.660Z", "dateReserved": "2024-06-13T14:41:01.525Z", "dateUpdated": "2024-12-09T15:03:06.924Z", "state": "PUBLISHED" }, "dataType": "CVE_RECORD", "dataVersion": "5.1" }
Mitigation
Phase: Architecture and Design
Description:
- Hardware designers may choose to engineer the processor's pipeline to prevent architecturally restricted data from being used by operations that can execute transiently.
Mitigation
Phase: Architecture and Design
Description:
- Hardware designers may choose not to share microarchitectural resources that can contain sensitive data, such as fill buffers and store buffers.
Mitigation
Phase: Architecture and Design
Description:
- Hardware designers may choose to sanitize specific microarchitectural state (for example, store buffers) when the processor transitions to a different context, such as whenever a system call is invoked. Alternatively, the hardware may expose instruction(s) that allow software to sanitize microarchitectural state according to the user or system administrator's threat model. These mitigation approaches are similar to those that address CWE-226; however, sanitizing microarchitectural state may not be the optimal or best way to mitigate this weakness on every processor design.
Mitigation
Phase: Architecture and Design
Description:
- The hardware designer can attempt to prevent transient execution from causing observable discrepancies in specific covert channels.
Mitigation
Phase: Architecture and Design
Description:
- Software architects may design software to enforce strong isolation between different contexts. For example, kernel page table isolation (KPTI) mitigates the Meltdown vulnerability [REF-1401] by separating user-mode page tables from kernel-mode page tables, which prevents user-mode processes from using Meltdown to transiently access kernel memory [REF-1404].
Mitigation
Phase: Build and Compilation
Description:
- If the weakness is exposed by a single instruction (or a small set of instructions), then the compiler (or JIT, etc.) can be configured to prevent the affected instruction(s) from being generated, and instead generate an alternate sequence of instructions that is not affected by the weakness.
Mitigation
Phase: Build and Compilation
Description:
- Use software techniques (including the use of serialization instructions) that are intended to reduce the number of instructions that can be executed transiently after a processor event or misprediction.
Mitigation
Phase: Implementation
Description:
- System software can mitigate this weakness by invoking state-sanitizing operations when switching from one context to another, according to the hardware vendor's recommendations.
Mitigation
Phase: System Configuration
Description:
- Some systems may allow the user to disable (for example, in the BIOS) sharing of the affected resource.
Mitigation
Phase: System Configuration
Description:
- Some systems may allow the user to disable (for example, in the BIOS) microarchitectural features that allow transient access to architecturally restricted data.
Mitigation
Phase: Patching and Maintenance
Description:
- The hardware vendor may provide a patch to sanitize the affected shared microarchitectural state when the processor transitions to a different context.
Mitigation
Phase: Patching and Maintenance
Description:
- This kind of patch may not be feasible or implementable for all processors or all weaknesses.
Mitigation
Phase: Requirements
Description:
- Processor designers, system software vendors, or other agents may choose to restrict the ability of unprivileged software to access to high-resolution timers that are commonly used to monitor covert channels.
No CAPEC attack patterns related to this CWE.