github - ghsa-m8m2-8cm8-p8jv

ghsa-m8m2-8cm8-p8jv

Vulnerability from github

Published

2023-10-19 12:30

Modified

2024-04-04 08:47

Severity ?

8.1 (High) - CVSS:3.1/AV:L/AC:L/PR:H/UI:N/S:C/C:L/I:H/A:H

Details

Motorola MTM5000 series firmwares lack properly configured memory protection of pages shared between the OMAP-L138 ARM and DSP cores. The SoC provides two memory protection units, MPU1 and MPU2, to enforce the trust boundary between the two cores. Since both units are left unconfigured by the firmwares, an adversary with control over either core can trivially gain code execution on the other, by overwriting code located in shared RAM or DDR2 memory regions.

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{
  "affected": [],
  "aliases": [
    "CVE-2022-27813"
  ],
  "database_specific": {
    "cwe_ids": [
      "CWE-1260"
    ],
    "github_reviewed": false,
    "github_reviewed_at": null,
    "nvd_published_at": "2023-10-19T10:15:10Z",
    "severity": "HIGH"
  },
  "details": "Motorola MTM5000 series firmwares lack properly configured memory protection of pages shared between the OMAP-L138 ARM and DSP cores. The SoC provides two memory protection units, MPU1 and MPU2, to enforce the trust boundary between the two cores. Since both units are left unconfigured by the firmwares, an adversary with control over either core can trivially gain code execution on the other, by overwriting code located in shared RAM or DDR2 memory regions.",
  "id": "GHSA-m8m2-8cm8-p8jv",
  "modified": "2024-04-04T08:47:37Z",
  "published": "2023-10-19T12:30:23Z",
  "references": [
    {
      "type": "ADVISORY",
      "url": "https://nvd.nist.gov/vuln/detail/CVE-2022-27813"
    },
    {
      "type": "WEB",
      "url": "https://tetraburst.com"
    }
  ],
  "schema_version": "1.4.0",
  "severity": [
    {
      "score": "CVSS:3.1/AV:L/AC:L/PR:H/UI:N/S:C/C:L/I:H/A:H",
      "type": "CVSS_V3"
    }
  ]
}

CVE-2022-27813 (GCVE-0-2022-27813)

Vulnerability from cvelistv5

Published

2023-10-19 09:34

Modified

2024-08-03 05:33

Severity ?

8.1 (High) - CVSS:3.1/AV:L/AC:L/PR:H/UI:N/S:C/C:L/I:H/A:H/E:F/RL:U/RC:C/MAV:L/MAC:L/MPR:H/MUI:N/MS:C/MC:L/MI:H/MA:H

CWE

CWE-1260 - Improper Handling of Overlap Between Protected Memory Ranges

Summary

Motorola MTM5000 series firmwares lack properly configured memory protection of pages shared between the OMAP-L138 ARM and DSP cores. The SoC provides two memory protection units, MPU1 and MPU2, to enforce the trust boundary between the two cores. Since both units are left unconfigured by the firmwares, an adversary with control over either core can trivially gain code execution on the other, by overwriting code located in shared RAM or DDR2 memory regions.

References

►

URL

Tags

https://tetraburst.com/

related

Impacted products

	Vendor	Product	Version
	Motorola	Mobile Radio	Version: MTM5000

Show details on NVD website

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{
  "containers": {
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        "metrics": [
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            "other": {
              "content": {
                "id": "CVE-2022-27813",
                "options": [
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                    "Exploitation": "none"
                  },
                  {
                    "Automatable": "no"
                  },
                  {
                    "Technical Impact": "partial"
                  }
                ],
                "role": "CISA Coordinator",
                "timestamp": "2024-07-15T15:42:18.505018Z",
                "version": "2.0.3"
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        "title": "CISA ADP Vulnrichment"
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        }
      ],
      "metrics": [
        {
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            "baseSeverity": "HIGH",
            "confidentialityImpact": "LOW",
            "integrityImpact": "HIGH",
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      "providerMetadata": {
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  "cveMetadata": {
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    "datePublished": "2023-10-19T09:34:44.148Z",
    "dateReserved": "2022-03-24T03:04:57.475Z",
    "dateUpdated": "2024-08-03T05:33:00.474Z",
    "state": "PUBLISHED"
  },
  "dataType": "CVE_RECORD",
  "dataVersion": "5.1"
}

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